This invention relates to semiconductor devices that comprise embedded conductive interconnects. More specifically, the present invention relates to static random access memory (SRAM) cells with conductive interconnects that are embedded in the substrate, as well as methods for fabricating such SRAM cells.
A static random access memory (SRAM) is a significant memory device due to its high speed, low power consumption, and simple operation. Unlike a dynamic random access memory (DRAM) cell, the SRAM does not need to regularly refresh the stored data and it has a straightforward design.
Each bit in a typical six-transistor SRAM (6T-SRAM) cell is stored on four transistors, generally referred to as load transistors (or pull-up transistors) and driver transistors (or pull-down transistors), that form a flip-flop circuit containing two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors (or pass-gate transistors) serve to control the access to a storage cell during read and write operations.
FIG. 1A shows a top-down view of an exemplary complementary metal-oxide-semiconductor (CMOS) 6T-SRAM cell underneath the first metal interconnect level (M1). The 6T-SRAM cell contains: (1) four active device regions (i.e., doped-well regions) 112, 114, 116, and 118, and (2) four gate structures 122, 124, 126, and 128, which form 6 typical metal-oxide-semiconductor (MOS) transistors 101-106. Specifically, n-channel pass-gate transistors 101 and 104 and n-channel pull-down transistors 102 and 103 are formed within the n-type active device regions 112 and 114, and p-channel pull-up transistors 105 and 106 are formed within the p-type active device regions 116 and 118. The active device regions 112, 114, 116, and 118 are formed within the same semiconductor substrate, which may preferably be a silicon substrate doped with n-type and p-type impurities in the vicinity of the p-channel transistors and the n-channel transistors, respectively. Gate structures 122 and 126 extend above the active device region 112 to form gates for the pull-down transistor 102 and the pass-gate transistor 101, respectively. Similarly, gate structures 124 and 128 extend above the active device region 114 to form gates for the pull-down transistor 103 and the pass-gate transistor 104, respectively. Further, the gate structures 122 and 124 extend to over the active device regions 116 and 118 to form gates for the pull-up transistors 105 and 106, respectively. Each SRAM cell further contains multiple metal contacts (CAs) for accessing the respective components of the transistors 101-106, as shown in FIG. 1A.
FIG. 1B shows a top-down view of the exemplary the SRAM cell of FIG. 1A at the M1 level, i.e., the first metal interconnect level. The SRAM cell at the M1 level contains multiple external interconnects or nodes (ENs) and internal interconnects or nodes (INs), each of which overlays one or more SRAM metal contacts (CAs) and forms electrical connections with the CAs. For example, the two ENs located at the middle left and right borders of the SRAM cell respectively overlay and form electrical connections with the CAs that overlay the gate structures 126 and 128 of the pass-gate transistors 101 and 104. The six ENs located at the upper and lower borders of the SRAM cell respectively overlay and form electrical connections with the CAs that overlay the source or drain regions of the transistors 101-106. The two INs located in the middle of the SRAM cell respectively cross-connect the pull-down transistors 102 and 103 with the pull-up transistors 105 and 106.
FIG. 1C shows a cross-sectional view of the SRAM cell along line I-I in FIG. 1B. The two ENs, which are located at the M1 level along the middle left and right borders of the SRAM cell, electrically connect the underlying CAs (not shown) at the contact level with metal vias 132 in the first via level (V1), which in turn are electrically connected to metal interconnects (not shown) in upper metal levels (not shown), such as M2, M3, . . . etc., and/or metal vias (not shown) in upper via levels (not shown), such as V2, V3, . . . etc. Each of the two INs, which are located in the M1 level at the middle portions of the SRAM cell, electrically connects one CA with another CA at the contact level. In this manner, the INs cross-connects the pull-down transistors 102 and 103 located at the active device regions 112 and 114 with the respective pull-up transistors 105 and 106 located at the active device regions 116 and 118 in the underlying substrate 110. Note that the surfaces of the active device regions 112, 114, 116 and 118 are silicided, thereby forming respective surface metal silicide layers 112S, 114S, 116S and 118S. The INs extend only along the M1 level and are not connected to any metal vias and/or interconnects in the upper via and/or metal levels. Therefore, the INs are also referred to hereinafter as “local interconnects.”
As the 45 nm node and the 32 nm node generations of complementary metal-oxide-semiconductor (CMOS) devices are approached, scaling of the SRAM cells becomes imperative. However, the scaling effort is significantly limited by conventional lithographic printing, which has been used for patterning the metal contacts and the metal interconnects of the SRAM cells. Due to the large number of metal contacts at the CA level and metal interconnects at the M1 level of the SRAM cells, the overlay limits of conventional lithographic printing have already been reached, and it is difficult to scale the SRAM cells to fit the space requirements of the 45 nm node and the 32 nm node generations.
Therefore, there is a need to reduce the number of metal contacts and metal interconnects in the SRAM cells, thus allowing further scaling of the SRAM cells for the 45 nm node and the 32 nm node generations.